The present invention relates generally to integrated circuit testing, and more particularly to a method and apparatus for non-contact testing and diagnosing of open connections of power and ground nodes on unpowered circuit devices.
During the manufacture of circuit assemblies such as printed circuit boards (PCBs), multi-chip modules (MCMs), or other packaging hierarchies, testing for interconnection defects such as open and shorted joints or interconnects is performed. Well-known capacitance lead-frame sensing technologies exist that can detect opens between the pins of an integrated circuit (IC) and the mounting substrate (typically a PCB). Typical implementation of capacitive probe assemblies that implement a capacitive sensor may be found in the following references, each of which is incorporated herein by reference for all that it teaches: U.S. Pat. No. 5,498,964, to Kerschner et al., entitled “Capacitive Electrode System for Detecting Open Solder Joints in Printed Circuit Assemblies”, U.S. Pat. No. 5,124,660 to Cilingiroglu, entitled “Identification of Pin-Open Faults By Capacitive Coupling Through the Integrated Circuit Package”, U.S. Pat. No. 5,254,953 to Crook et al., entitled “Identification of Pin-Open Faults By Capacitive Coupling Through the Integrated Circuit Package”, and U.S. Pat. No. 5,557,209 to Crook et al., entitled “Identification of Pin-Open Faults By Capacitive Coupling Through the Integrated Circuit Package”.
U.S. Publication No. 20050242824 A1 published Nov. 3, 2005 and entitled “Methods And Apparatus For Non-Contact Testing And Diagnosing Open Connections For Connectors on Printed Circuit Boards” to Parker et al., incorporated herein by reference for all that it teaches, and assigned to the assignee of interest herein provides a method for testing for open power and ground connections in connectors and sockets, by making use of the inherently available coupling capacitors that exist between connector pins. When a signal pin is tested that is coupled to a nearby ground pin, an open on that ground pin will cause the signal pin measurement to rise in value.
For better understanding of the invention, a brief introduction to capacitive lead frame testing techniques is now presented. Turning to the drawings, FIG. 1A shows the basic setup and FIG. 1B shows the equivalent circuit model of capacitive lead-frame testing for open signal pins on an electrical circuit device embodied by an integrated circuit.
As shown, an integrated circuit (IC) die 18 is packaged in an IC package 12. The package 12 includes a lead frame 14 supporting a plurality of pins 10a, 10b. Pads of the IC die 18 are connected to the package pins 10a, 10b at the lead frame 14 via bond wires 16a, 16b. The pins 10a, 10b are supposed to be conductively attached, for example by way of solder joints, to pads 8a, 8b of a printed circuit board (PCB) 6. The test setup shown in FIG. 1A determines whether package pins are properly connected to the board at the solder joints. The test setup includes an alternating current (AC) source 2 that applies an AC signal, through a test probe 4a (and possibly other intervening circuitry, for example tester fixture adapters), to a node connected to the pad 8a on the PCB 6 to which a pin under test 10a should be electrically connected. In a typical test environment, the AC signal is typically 8192 Hz at 0.2 volts. A capacitive sensing probe 20 comprising a conductive sense plate 22 and amplifying buffer 24 is placed on top of the integrated circuit package 12. The capacitive sensing probe 20 is connected to a current measuring device 26, such as an ammeter. Another pin 10b of the integrated circuit 12 is connected to a circuit ground via a grounded probe 4b. 
When the test is performed, the AC signal applied to pad 8a appears on the pin 10a of the integrated circuit package 12. Through capacitive coupling, in particular a capacitance Csense formed between the lead frame 14 and sense plate 22, a current Is is passed to the sense plate 22 and then through the amplifying buffer 24 to the current measuring device 26. If the measured current Is falls between predetermined limits, then the pin 10a is properly connected to the pad 8a. If the pin 10a is not connected to the pad 8a, a capacitance Copen is formed between the pad 8a and pin 10a, altering the current Is measured by the current measuring device 26 such that the measured current Is falls outside the predetermined limits, thereby indicating that an open defect is present at the pin connection.
The above approaches focus on detection of open conditions on signal nodes of an integrated circuit device. It is well-known in the art that source power and ground connections of a circuit should be bypassed typically with bypass capacitors or dampening resistors in order to reduce signal variations on the circuit power source. Accordingly, during a capacitive lead frame test, the source power and ground nodes are typically grounded by the tester in order to remove the effects of the bypass elements from the test measurement setup. Because they must be grounded, source power and ground nodes cannot be tested using the standard capacitive sensing technique described above. Accordingly, it would be desirable to have a technique for applying capacitive sensing testing techniques to the detection of open defects on power and ground pins of a device.
In addition, many discrete components that may be connected on a PCB do not lend themselves easily to standard capacitive leadframe testing. FIG. 2A shows an electrical schematic of a discrete Field Effect Transistor (FET) 30, and FIG. 2B shows a physical packaged FET device 35 that may be discretely mounted on a PCB 38 or other such substrate. FETs such as that shown in FIGS. 2A and 2B are often mounted on PCBs 38 for the purpose of regulating and/or generating power supplies. Such FETs are often comparatively large to support high current capacity and heat dissipation, and often have integral heat sinks 36 that are bolted 37 to the board 38, as shown in FIG. 2B.
Currently known testing techniques for determining connectivity of terminals of discrete FET devices mounted on boards include In-Circuit measurement of drain-to-source impedance. Capacitive leadframe testing may also be performed on the gate terminal; however, because the drain 33 and source 31 terminals are typically bypassed (with a bypass capacitor or dampening resistor), prior capacitive leadframe testing only tested for gate 32 connectivity. Other testing techniques may involve turning on power to measure the effect of turning on/off the FET. Each of these tests have varying disadvantages and lack of coverage. Turning on power may be especially troublesome since the board may be defective and subject to damage.
Individual FET devices may also be connected in parallel to boost current capacity of the circuit design. Accordingly, their terminals may be ganged, drain-to-drain, source-to-source, and gate-to-gate. In this configuration, conventional electrical tests for these FET devices are not able to detect open connections at the terminals since there are parallel paths for current flow. Waiting until a functional test stage (where power must be turned on) to find FET defects may be risky. Accordingly, a need also exists for an unpowered method to find open defects on all FET terminals, regardless of single or parallel FET connections.